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Subsurface Defect Localization by Structured Heating Using Laser Projected Photothermal Thermography

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Wafer Defect Detection Technology Based on CTM-IYOLOv10 Network.

Pengcheng Ji¹, Zhenzhi He¹, Weiwei Yang²

¹School of Mechanical and Electrical Engineering, Jiangsu Normal University, Xuzhou 221116, China.

Journal of Imaging

|November 26, 2025

Summary

This summary is machine-generated.

This study introduces an improved YOLOv10 network (CTM-IYOLOv10) for semiconductor wafer defect detection. The new method enhances accuracy and efficiency, significantly improving intelligent manufacturing processes.

Keywords:

YOLOv10 clustering–template matching intelligent manufacturing real-time industrial inspection small object detection wafer defect detection

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Area of Science:

Semiconductor Manufacturing
Artificial Intelligence
Computer Vision

Background:

Semiconductor device scaling increases wafer die complexity, necessitating advanced defect detection.
Traditional inspection methods are inefficient and prone to errors, especially for small defects.

Purpose of the Study:

To develop an efficient and accurate wafer defect detection framework for intelligent manufacturing.
To improve upon existing deep learning models for detecting small and irregular defects on semiconductor wafers.

Main Methods:

Integration of clustering-template matching (CTM) with an improved YOLOv10 network (CTM-IYOLOv10).
Implementation of a modified GhostConv module and enhanced BiFPN for improved feature representation and small-object detection.
Application of data augmentation strategies to enhance model robustness and generalization.

Main Results:

CTM-IYOLOv10 achieved 98.1% detection accuracy, outperforming YOLOv5 and YOLOv8.
Reduced inference time by 23.2% and model size by 52.3% compared to baseline YOLOv10.
Demonstrated enhanced die segmentation efficiency and mitigation of redundant matching.

Conclusions:

The CTM-IYOLOv10 framework offers significant improvements in accuracy, speed, and model size for wafer defect inspection.
The proposed architecture provides a practical and effective solution for real-time defect detection in semiconductor manufacturing.