Wafer Defect Detection Technology Based on CTM-IYOLOv10 Network

The continuous scaling of semiconductor devices has increased the density and complexity of wafer dies, making precise and efficient defect detection a critical task for intelligent manufacturing. Traditional manual or semi-automated inspection approaches are often inefficient, error-prone, and susceptible to missed or false detections, particularly for small or irregular defects. This study presents a wafer defect detection framework that integrates clustering-template matching (CTM) with an improved YOLOv10 network (CTM-IYOLOv10). The CTM strategy enhances die segmentation efficiency and mitigates redundant matching in multi-die fields of view, while the introduction of a modified GhostConv module and an enhanced BiFPN structure strengthens feature representation, reduces computational redundancy, and improves small-object detection. Furthermore, data augmentation strategies are employed to improve robustness and generalization. Experimental evaluations demonstrate that CTM-IYOLOv10 achieves a detection accuracy of 98.1%, reduces inference time by 23.2%, and compresses model size by 52.3% compared with baseline YOLOv10, and consistently outperforms representative detectors such as YOLOv5 and YOLOv8. These results highlight both the methodological contributions of the proposed architecture and its practical significance for real-time wafer defect inspection in semiconductor manufacturing.