Ferroelectric transistors for low-power NAND flash memory

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Engineering

Background:

• NAND flash memory is crucial for modern storage, driven by AI and data-centric computing.
• Its series 'string' architecture necessitates high-voltage operations, leading to significant power consumption.
• Reducing pass voltage in NAND flash limits memory window and multi-level operation.

Purpose of the Study:

• To develop ultralow-power ferroelectric field-effect transistors (FeFETs) that overcome the limitations of conventional NAND flash memory.
• To achieve high multi-level cell capability with significantly reduced power consumption.
• To demonstrate the feasibility of scaled, 3D-integrated FeFETs for next-generation storage.

Main Methods:

• Fabrication of FeFETs utilizing a gate stack of zirconium-doped hafnia and an oxide semiconductor channel.
• Characterization of FeFET electrical properties, including memory window and pass voltage.
• 3D integration of FeFET stacks into vertical structures with a 25-nm channel length.

Main Results:

• FeFETs demonstrate up to 5-bit per cell multi-level capability, comparable to or exceeding current NAND technology.
• Achieved nearly zero pass voltage, resulting in up to 96% power savings in string-level operations.
• 3D-integrated FeFETs maintain robust electrical properties at scaled dimensions, showing low-pass-voltage string operation.

Conclusions:

• The developed FeFETs offer a solution to the power consumption dilemma in NAND flash memory.
• These FeFETs pave the way for next-generation storage memory with enhanced capacity, power efficiency, and reliability.
• The technology is suitable for scaled dimensions and 3D integration, crucial for future storage advancements.