DLL Design with Wide Input Duty Cycle Range and Low Output Clock Duty Cycle Error

This paper presents the design of a Delay-Locked Loop (DLL) with a simple architecture and a wide input clock duty cycle range. The design is tailored to meet the increasing data rate and stringent clock requirements of modern semiconductor chips, with particular applicability to dynamic random-access memory (DRAM) systems. The structure features two Bang-Bang Phase Detectors (BBPDs) to adjust the rising and falling edges of the divided clock. Implemented using a 65 nm CMOS process, the design was verified through simulation. At a working frequency of 3.2 GHz, the input clock duty cycle range spans from 18% to 72%, with a maximum output clock duty cycle error of just 0.6%, a peak-to-peak jitter of 15.73 ps, and a power consumption of 12.7 mW.