DLL Design with Wide Input Duty Cycle Range and Low Output Clock Duty Cycle Error

Area of Science:

• Electrical Engineering
• Computer Engineering
• Microelectronics

Background:

• Modern semiconductor chips demand higher data rates and precise clock signals.
• Existing Delay-Locked Loop (DLL) designs often struggle with wide input clock duty cycle variations.
• Dynamic Random-Access Memory (DRAM) systems require robust clocking solutions.

Purpose of the Study:

• To present a novel DLL architecture with a simple design.
• To achieve a wide input clock duty cycle range for enhanced applicability.
• To meet the stringent clock requirements of high-speed semiconductor applications.

Main Methods:

• Designed a DLL utilizing two Bang-Bang Phase Detectors (BBPDs).
• The BBPDs are employed to independently adjust the rising and falling edges of the divided clock signal.
• Implementation and verification were performed using a 65 nm CMOS process through simulation.

Main Results:

• The DLL operates at a frequency of 3.2 GHz.
• Achieved a wide input clock duty cycle range from 18% to 72%.
• Demonstrated a low maximum output clock duty cycle error of 0.6%, peak-to-peak jitter of 15.73 ps, and power consumption of 12.7 mW.

Conclusions:

• The proposed DLL design offers a simple yet effective solution for wide duty cycle clock synchronization.
• The design is well-suited for high-speed applications, including DRAM, due to its performance metrics.
• This work contributes a valuable clocking component for next-generation semiconductor integrated circuits.