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Related Experiment Video

Updated: Jan 9, 2026

Fabrication and Characterization of High-Q Silicon Nitride Membrane Resonators
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Low-Temperature Laser-Crystallized Silicon Nanosheet Field Effect Transistors Enabling Monolithic 3D Integration.

Jeong Yeon Im1, Hanbin Lee1, So-Jeong Park1

  • 1School of Electrical Engineering, Kookmin University, Seoul 02707, Korea.

ACS Applied Materials & Interfaces
|December 9, 2025
PubMed
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We developed a low-temperature silicon nanosheet transistor fabrication method using laser annealing. This technique enables advanced 3D integration by crystallizing silicon and activating dopants in a single step, crucial for future electronics.

Area of Science:

  • Semiconductor device fabrication
  • Materials science
  • Nanotechnology

Background:

  • Monolithic three-dimensional (3D) integration requires low-thermal-budget fabrication processes.
  • Conventional methods for silicon crystallization and dopant activation often exceed thermal limits for 3D architectures.

Purpose of the Study:

  • To develop a low-temperature fabrication strategy for silicon nanosheet (SiNS) field-effect transistors (FETs).
  • To enable integration of SiNS FETs into monolithic 3D (M3D) architectures using a simplified process.
  • To optimize laser annealing parameters for high-performance devices.

Main Methods:

  • Utilized amorphous silicon (a-Si) as the channel material.
  • Employed single-step nanosecond pulsed Nd:YAG laser annealing for simultaneous crystallization and dopant activation.
Keywords:
Nd:YAG laser annealingcrystallinityhomogeneous nucleationlow-temperature processmonolithic 3D integrationsilicon nanosheet FET

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  • Controlled laser fluence to optimize crystalline quality and electrical properties.
  • Conducted structural (TEM) and electrical analyses (interface trap density, series resistance).

    • Main Results:

    • Achieved simultaneous crystallization and source/drain dopant activation of a-Si within a sub-450 °C thermal budget.
    • Optimized laser fluence to minimize interface trap density and improve carrier mobility and subthreshold swing.
    • Demonstrated laser-annealed devices with performance comparable to conventionally processed transistors.
    • Verified minimal thermal diffusion to underlying layers.

    Conclusions:

    • The developed laser annealing technique is a scalable and thermally compatible method for fabricating SiNS FETs.
    • This approach addresses key constraints for M3D integration, enabling high-performance logic devices in future 3D semiconductor systems.