Low-Temperature Laser-Crystallized Silicon Nanosheet Field Effect Transistors Enabling Monolithic 3D Integration.

Area of Science:

• Semiconductor device fabrication
• Materials science
• Nanotechnology

Background:

• Monolithic three-dimensional (3D) integration requires low-thermal-budget fabrication processes.
• Conventional methods for silicon crystallization and dopant activation often exceed thermal limits for 3D architectures.

Purpose of the Study:

• To develop a low-temperature fabrication strategy for silicon nanosheet (SiNS) field-effect transistors (FETs).
• To enable integration of SiNS FETs into monolithic 3D (M3D) architectures using a simplified process.
• To optimize laser annealing parameters for high-performance devices.

Main Methods:

• Utilized amorphous silicon (a-Si) as the channel material.
• Employed single-step nanosecond pulsed Nd:YAG laser annealing for simultaneous crystallization and dopant activation.
• Controlled laser fluence to optimize crystalline quality and electrical properties.
• Conducted structural (TEM) and electrical analyses (interface trap density, series resistance).

Main Results:

• Achieved simultaneous crystallization and source/drain dopant activation of a-Si within a sub-450 °C thermal budget.
• Optimized laser fluence to minimize interface trap density and improve carrier mobility and subthreshold swing.
• Demonstrated laser-annealed devices with performance comparable to conventionally processed transistors.
• Verified minimal thermal diffusion to underlying layers.

Conclusions:

• The developed laser annealing technique is a scalable and thermally compatible method for fabricating SiNS FETs.
• This approach addresses key constraints for M3D integration, enabling high-performance logic devices in future 3D semiconductor systems.