Efficient total ionizing dose-aware standard cell characterization methodology for path-level timing performance in...

As CMOS technology scales into the nanoscale regime, ensuring the reliability of digital circuits in radiation-rich environments has become a critical challenge. Standard cell libraries, which are foundational to digital design, are typically characterized using extensive SPICE simulations to capture gate delays as functions of input transition time and load capacitance. However, these libraries do not account for total ionizing dose (TID) effects, which are caused by prolonged exposure to ionizing radiation and introduce oxide-trapped charges and interface states that degrade key transistor parameters, such as threshold voltage and leakage current. This results in significant timing inaccuracies, compromising digital timing closure in mission-critical applications such as aerospace and nuclear electronics. In this work, we propose an efficient, TID-aware standard cell characterization methodology for nanoscale CMOS technologies that generates cell characterization data in standard Liberty format, enabling accurate prediction of timing closure under TID influence without incurring any SPICE simulation overhead. Our approach leverages well-calibrated 32 nm Synopsys^©Sentaurus TCAD simulations and variation-aware analytical timing models to capture TID-induced degradation. These effects are incorporated into cell netlists through adjustments to the BSIM parameters to generate both pre- and post-radiation standard cell libraries. Validated using a set of reference designs, including ISCAS benchmark circuits, the proposed methodology achieves accurate path-level timing predictions under radiation while reducing SPICE simulation effort by approximately 81.25%. By bridging device-level radiation effects with cell-level timing abstraction, this scalable framework offers a practical solution for robust and radiation-resilient digital integrated circuit design in harsh environments.