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A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
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Efficient total ionizing dose-aware standard cell characterization methodology for path-level timing performance in
Lomash Chandra Acharya1, Khoirom Johnson Singh2, Neha Gupta1
1Microelectronics and VLSI Group, Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, Uttarakhand 247667, India.
Nanotechnology
|December 9, 2025
Summary
This study introduces a novel method for characterizing standard cells in nanoscale CMOS circuits, accounting for Total Ionizing Dose (TID) effects. The approach ensures accurate timing predictions in radiation environments, enhancing digital circuit reliability.
Area of Science:
- Electrical Engineering
- Materials Science
- Computer Engineering
Background:
- Nanoscale CMOS technology faces reliability challenges in radiation-rich environments.
- Standard cell libraries lack Total Ionizing Dose (TID) effect characterization.
- TID degrades transistor parameters, causing timing inaccuracies in critical applications.
Purpose of the Study:
- To develop an efficient, TID-aware standard cell characterization methodology.
- To generate radiation-resilient cell characterization data in Liberty format.
- To enable accurate timing closure prediction under TID influence without SPICE overhead.
Main Methods:
- Utilized 32 nm Synopsys© Sentaurus TCAD simulations for TID effect modeling.
- Employed variation-aware analytical timing models to capture radiation-induced degradation.
- Adjusted BSIM parameters in cell netlists to create pre- and post-radiation libraries.
Main Results:
- Achieved accurate path-level timing predictions for reference designs under radiation.
- Reduced SPICE simulation effort by approximately 81.25%.
- Generated TID-aware standard cell libraries in Liberty format.
Conclusions:
- The proposed methodology provides a practical solution for radiation-resilient digital IC design.
- Bridged device-level radiation effects with cell-level timing abstraction.
- Ensures robust digital circuit performance in harsh environments like aerospace and nuclear electronics.
Keywords:
TID-aware delay dataTID-aware timing closurenanoscale CMOSstandard cell characterizationtotal ionizing dose (TID)variation-aware timing modelMore Related Videos
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