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A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Beyond Silicon Frontiers in Neuromorphic Computing and Logic Circuits: Single-Walled Carbon Nanotube Thin-Film
Dinh Cung Tien Nguyen1, Balaji Murugan1, Chun Fei Siah1
1Department of Electrical and Computer Engineering, College of Design and Engineering, National University of Singapore, 117608, Singapore.
Abstract:
Inspired by the brain's parallel and energy-efficient processing, research into neuromorphic computing chips has increasingly explored the integration of thin-film transistors (TFTs) as artificial neuron-like elements, owing to their intrinsic three-terminal architecture, which enables synaptic behavior, low-power switching, and scalable integration for high-performance electronic systems. As research advances from individual device functionality toward system-level implementation, TFT-based neuromorphic computing and logic circuits have emerged as promising platforms for next-generation electronics, including wearable and implantable devices, neuromorphic components such as artificial synapses and electronic skin, and integrated logic architectures. To realize these TFT-based circuits, selecting materials with appropriate electrical properties is essential, and single-walled carbon nanotubes (SWCNTs) offer notable advantages over leading commercial backplane semiconductors: they exhibit ∼10× higher carrier mobility than IGZO, a representative oxide semiconductor widely used in high-end TV displays; ∼300× faster logic switching than conventional oxide TFTs, widely employed in advanced display systems; and subnanosecond signal delays at battery-compatible voltages (∼2.6 V), in contrast to the 10-15 V required for IGZO and ∼3 V for polycrystalline silicon, the prevalent choice in high-performance mobile displays. These electronic advantages are complemented by low-power consumption, excellent mechanical flexibility and stretchability, intrinsic biocompatibility, and the potential for large-area integration. Despite these promising attributes, the current SWCNT TFT technology ecosystem remains largely at Technology Readiness Levels 3-5, with most demonstrations limited to proof-of-concept devices and laboratory-scale prototypes, despite recent milestones such as semiconducting purities exceeding 99.9999%, scalable roll-to-roll processing, and high-density integration. In this Perspective, a strategic perspective is presented on advancing SWCNT TFTs from laboratory-scale innovations to scalable, industry-relevant platforms for neuromorphic and logic applications, with key technical challenges and development pathways outlined for their integration into practical intelligent electronic systems.
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