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Monolithically integrated 4 × 128 Gb/s, 3.07 pJ/bit silicon photonic transceiver for co-packaged optics
Optics Express
|December 19, 2025
Summary
This study introduces a novel silicon chip integrating optical and electronic components, enabling faster, more energy-efficient data transmission for AI and computing. This monolithic approach overcomes limitations of traditional methods for high-speed optical interconnects.
Area of Science:
- Photonics and Optical Communications
- Integrated Circuits and Systems
- Data Center Interconnects
Background:
- Data center traffic is rapidly increasing due to AI and high-performance computing.
- Current packaging methods for optical interconnects have parasitic effects limiting bandwidth and energy efficiency.
Purpose of the Study:
- To develop a monolithically integrated electronic-photonic transceiver on a silicon platform.
- To overcome limitations of conventional bonding processes in optoelectronic integration.
Main Methods:
- Fabrication of a single-chip transceiver on a 45nm CMOS-SOI platform.
- Co-design of Mach-Zehnder modulator (MZM), driver amplifier, Ge-Si photodetector (PD), and transimpedance amplifier (TIA).
- Elimination of bonding interfaces for improved signal integrity.
Main Results:
- Achieved 64 Gbaud PAM-4 data transmission below FEC thresholds for both transmitter and receiver.
- Demonstrated a total power consumption of 3.07 pJ/bit at 128 Gb/s.
- Significantly reduced parasitic effects by eliminating bonding interfaces.
Conclusions:
- Silicon-based monolithic optoelectronic integration offers a scalable solution for high-speed optical communication.
- This technology enhances system performance and energy efficiency for data centers.
- Paves the way for next-generation optical interconnects.
