Monolithically integrated 4 × 128 Gb/s, 3.07 pJ/bit silicon photonic transceiver for co-packaged optics

The exponential growth of data center traffic, driven by artificial intelligence (AI) and high-performance computing, demands optical interconnect solutions that overcome the limitations of current packaging integration methods. The conventional bonding process often suffers from substantial parasitic effects, which degrade signal integrity and limit both bandwidth scalability and energy efficiency. Here, we present a monolithically integrated electronic-photonic transceiver fabricated for a 45 nm CMOS-SOI platform, featuring a co-designed Mach-Zehnder modulator (MZM), driver amplifier, Ge-Si photodetector (PD), and transimpedance amplifier (TIA) within a single chip. By eliminating bonding interfaces in optoelectronic integration, the transmitter achieves a 64 Gbaud four-level pulse amplitude modulation (PAM-4) data transmission below the 5.8% overhead hard-decision (HD) forward error correction (FEC) bit error rate (BER) threshold of 3.8 × 10^-3, while the receiver achieves a 64 Gbaud PAM-4 data transmission below the 6.7% overhead KP4-FEC threshold of 2.4 × 10^-4. The integrated tranceivers consume the total power consumption of 3.07 pJ/bit at 128 Gb/s. This work highlights the potential of silicon-based monolithic optoelectronic integration techniques for high-speed optical communication and interconnection, offering remarkable enhancements in system performance and scalability.