Inverse-designed monolithic photonic logic gates: multifunctionality and combinational circuit simplification

Owing to its inherent advantages in high-speed operation and low power consumption, photonic computing has emerged as a promising pathway to surpass the performance bottlenecks of conventional electronic computing. However, most existing photonic logic devices continue to face critical challenges, including limited integration density and substantial redundancy in combinational logic structures. In this work, we integrate an inverse design framework with the principle of coherent light superposition to realize multifunctional monolithic photonic logic gates on a silicon-on-insulator (SOI) platform through a structure-function co-optimization approach. Complementary logic functions (NOT/BUF, AND/NAND, and OR/NOR) are synchronously integrated within a single device, achieving a 200% increase in on-chip functional density. Furthermore, we demonstrate, for the first time, the direct implementation of high-order optical combinational logic-specifically, half-adders and 2-to-4 decoders within a monolithic structure, effectively eliminating cascading redundancy and substantially reducing the spatial footprint of optical logic gates. A staged optimization strategy is employed to realize optical XOR and XNOR gates via two-level cascading, providing a viable approach for constructing more complex optical combinational logic circuits. Our work thus establishes a scalable design paradigm for highly integrated digital photonic computing chips.