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Updated: Jan 8, 2026

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds
Published on: December 2, 2013
Complementary Doping Strategy for Achieving Low Contact-Resistance in p-Type Two-Dimensional Field-Effect
Mayukh Das1, Krishnendu Mukhopadhyay1, Md Sajjad Alam2
1Engineering Science and Mechanics, Penn State University, University Park, Pennsylvania 16802, United States.
Researchers reduced contact resistance in p-type two-dimensional (2D) field-effect transistors (FETs) using complementary doping and a van der Waals interface. This breakthrough enhances 2D FET performance for logic circuits.
Area of Science:
- Materials Science
- Nanotechnology
- Semiconductor Physics
Background:
- High-performance complementary logic circuits require low contact resistance (R_C) in two-dimensional (2D) field-effect transistors (FETs).
- Achieving low R_C in p-type 2D FETs is challenging due to significant Schottky barriers for hole injection, unlike their n-type counterparts.
Purpose of the Study:
- To reduce R_C in p-type monolayer WSe2 FETs to the sub-kΩ·μm range.
- To engineer both the contact and channel regions for efficient hole injection.
- To narrow the performance gap between n-type and p-type 2D transistors.
Main Methods:
- Utilized degenerately Ta-doped multilayer MoSe2 as a p-type contact material laminated onto MOCVD-grown WSe2 channels.
- Employed a postfabrication NO anneal for selective channel doping via NO chemisorption at Se-vacancy sites.
- Combined complementary doping with a clean 2D/2D van der Waals (vdW) interface.
Main Results:
- Achieved R_C in the sub-kΩ·μm range for p-type monolayer WSe2 FETs.
- Demonstrated efficient hole injection, leading to high ON-current (I_ON) values up to 53 μA/μm.
- Preserved the contact properties of the Ta-doped MoSe2 while doping the WSe2 channel.
Conclusions:
- The presented strategy successfully reduces R_C in p-type 2D FETs by combining contact and channel engineering.
- This approach significantly advances the development of complementary 2D logic technologies.
- The method provides a pathway for balanced performance in n-type and p-type 2D transistors.
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