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Multi-stage decimation with hybrid CIC-polyphase filtering for IoT gateway sample rate conversion.

Swetha Pinjerla1, Surampudi Srinivasa Rao2, P Chandrasekhar Reddy3

  • 1Department of ECE, Jawaharlal Nehru Technological University, Hyderabad, India. pswetha0823@gmail.com.

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Summary

This study introduces an efficient multi-stage hybrid polyphase Cascaded Integrator-Comb (CIC) filter for real-time digital signal processing. The novel FPGA implementation significantly reduces hardware resource utilization while enhancing performance for wireless applications.

Keywords:
Cascaded integrator-combDecimation filtersFPGAPolyphaseVirtex

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Area of Science:

  • Digital Signal Processing
  • Hardware Acceleration
  • Wireless Communications

Background:

  • Multirate transformations, including decimation using comb-based filters like the Cascaded Integrator-Comb (CIC) filter, are crucial for real-time digital signal processing in wireless applications.
  • CIC filters offer advantages in speed and hardware efficiency due to their multiplier-less design, making them suitable for resource-constrained environments.
  • Optimizing digital filtering is essential for modern wireless systems demanding high throughput and low latency.

Purpose of the Study:

  • To present a novel multi-stage hybrid polyphase CIC filter architecture implemented on a Xilinx Virtex-4 Field-Programmable Gate Array (FPGA).
  • To enhance signal processing performance by integrating a polyphase CIC filter with an FIR compensation filter to mitigate passband droop and improve frequency response.
  • To demonstrate significant hardware savings and improved efficiency for high-speed wireless applications and Software-Defined Radio (SDR)-based IoT gateways.

Main Methods:

  • Implementation of a multi-stage hybrid polyphase CIC filter architecture on an FPGA.
  • Integration of a Finite Impulse Response (FIR) compensation filter to correct frequency response deviations.
  • Application of polyphase decomposition and pipeline optimization techniques to reduce computational complexity and latency.

Main Results:

  • The proposed FPGA-based filter achieves superior filtering performance compared to conventional CIC filters.
  • Significant hardware resource reduction was observed: up to 54% fewer Slice Registers, 94% fewer LUTs, and 88% fewer DSPs compared to prior works.
  • The design ensures low latency, high throughput, and efficient hardware utilization, validated by experimental results.

Conclusions:

  • The multi-stage hybrid polyphase CIC filter architecture provides a robust and efficient solution for real-time digital signal processing in wireless systems.
  • The FPGA implementation offers substantial hardware savings and performance enhancements, making it ideal for demanding applications like SDR-based IoT gateways.
  • This work highlights the effectiveness of combining polyphase decomposition and FIR compensation for advanced digital filter design.