Atomic Layer-by-Layer Lithography With Step-Terrace Topography Control via Selective Catalytic Reactions

Topography control with a depth precision down to single atomic layer is of paramount significance for advanced electronics with unique functionalities. Atomic step-terrace topography, representing the minimal vertical lattice unit, has been widely recognized as direct indicators of surface integrity and manufacturing precision, which significantly influences epitaxial growth, interfacial reactions, carrier transport, and defect evolution. However, achieving integrity and control of step-terrace topography becomes a challenging task for existing micro/nanopatterning technologies. Here, the flow-bunching evolution of step-terrace topography during atomic layer-by-layer lithography is proposed and experimentally demonstrated, where the catalytic etching priority is determined by terrace type and dangling bond number with high selectivity. Taking 4H-SiC (0001) as example, by applying a pulse bias to a catalytically active probe under ambient conditions, atomic layer-by-layer lithography is achieved while preserving the periodic step-terrace topography. High-angle annular dark field scanning transmission electron microscopy images reveal that the etched regions retain the perfect crystallographic order, with no detectable subsurface damage. Based on proposed flow-bunching evolution process, material removal can be controlled down to single Si-C atomic bilayer precision (∼2.5 Å in thickness). This work demonstrates a strategy to achieve atomically ordered topography, offering a promising pathway toward extreme-precision patterning for advanced semiconductor devices.