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High-Throughput and Memory-Efficient Pipeline Key-Value Store Architecture on FPGA.

Xinshuo Wang^1,2, Lei Liu^1,2, Yifei Li^1,2

¹National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, China.

|December 31, 2025

Summary

This study presents an FPGA-based Key-Value Store (KVS) to boost network security performance. The novel multi-level multi-hash design achieves high throughput and memory efficiency for demanding network applications.

Keywords:

FPGA KVS hardware acceleration parallel pipelined

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Area of Science:

Computer Engineering
Network Security
Hardware Acceleration

Background:

Increasing network speeds necessitate high-performance network security and monitoring systems.
Key-Value Stores (KVSs) are crucial components in modern network security applications.
Existing KVS solutions face challenges in throughput and storage utilization.

Purpose of the Study:

To propose and implement an FPGA-based KVS architecture.
To enhance KVS performance, specifically throughput and memory utilization.
To address limitations of current KVS designs in high-speed network environments.

Main Methods:

Developed a multi-level multi-hash approach for FPGA implementation.
Utilized a decoupled storage design for improved memory efficiency.
Implemented a pipeline scheme to maximize operational throughput.

Main Results:

Achieved over 95% memory utilization with decoupled storage.
Reached a high performance of 400 million requests per second (MRPS).
Maintained low latency for insert, query, and delete operations at 60 ns.

Conclusions:

The proposed FPGA-based KVS effectively handles skewed workloads and avoids false misses/inserts.
This architecture offers a significant performance and power efficiency improvement for network security systems.
The design meets the growing demands of high-speed network traffic for KVS performance.