Engineering Negative Capacitance in Hf_0.5Zr_0.5O₂ for Low-Power and Reliable Charge Trap Flash Memory

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Devices

Background:

• Charge trap flash (CTF) memory is crucial for high-density nonvolatile memory.
• High operating voltages in CTF memory cause reliability issues like interference and dielectric breakdown, hindering 3D scaling.

Purpose of the Study:

• To develop a negative capacitance charge trap flash (NC-CTF) memory with enhanced efficiency and reliability.
• To enable low-voltage program/erase (PGM/ERS) operations through capacitance boosting.

Main Methods:

• Engineered a Hf0.5Zr0.5O2 (HZO) layer by incorporating a dielectric interlayer (IL) to strengthen the negative capacitance (NC) effect.
• Utilized AlN as the IL material and a superlattice deposition process for HZO to enhance ferroelectricity and oxygen vacancy formation.
• Embedded the engineered NC layer into the blocking oxide (BO) of the CTF device.

Main Results:

• Achieved remarkable operation efficiency via NC-induced capacitance boosting effect of the engineered HZO layer.
• Demonstrated low-voltage PGM/ERS operations by modulating HZO domain configuration and enhancing depolarization energy.
• Improved ferroelectricity at halved HZO thickness and addressed reliability concerns, including cell-to-cell interference and dielectric breakdown.

Conclusions:

• The engineered NC-CTF memory offers a promising solution for next-generation nonvolatile memory.
• Synergistic improvements in efficiency and reliability pave the way for practical implementation.
• Low-voltage operation and enhanced endurance are key benefits for high-density memory scaling.