Gate structuring on n-type bilayer MoS₂ field-effect transistors for ultrahigh current density

Area of Science:

• Materials Science
• Semiconductor Physics
• Nanotechnology

Background:

• Moore's Law scaling for silicon transistors faces physical limitations, necessitating exploration of alternative materials and device architectures.
• Two-dimensional (2D) semiconductors, like molybdenum disulfide (MoS2), offer potential for continued miniaturization due to their atomic thinness and preserved crystalline quality.
• Existing 2D field-effect transistors (FETs) face challenges in achieving performance parity with silicon, particularly concerning carrier mobility and fabrication complexity.

Purpose of the Study:

• To investigate the potential of dual-gate bilayer MoS2 FETs as a viable alternative to silicon-based logic transistors.
• To mitigate performance bottlenecks in 2D FETs, specifically the fringing-field barrier caused by elevated contacts.
• To demonstrate high carrier densities and drain currents in MoS2 FETs without escalating fabrication complexity.

Main Methods:

• Fabrication of dual-gate bilayer MoS2 FETs utilizing conventional gold contacts.
• Implementation of simulations and statistical analysis to evaluate device performance and understand underlying physics.
• Quantum-transport simulations to project future performance under scaled dimensions and advanced integration schemes.

Main Results:

• The dual-gate structure effectively compensates for the fringing-field effect, enabling a significant drain current of 1.55 mA/µm.
• High carrier densities were achieved without introducing complex fabrication steps, maintaining practical manufacturability.
• Simulations predict that scaled MoS2 FETs can achieve on-state currents comparable to 3-nm node silicon FETs.

Conclusions:

• Dual-gate bilayer MoS2 FETs present a promising pathway for overcoming the limitations of Moore's Law in logic transistor scaling.
• The demonstrated approach offers a route to high-performance 2D transistors with manageable fabrication complexity.
• Monolithic 3D integration of these dual-gate 2D transistors can extend their applicability to future generations of logic technology.