Gate structuring on n-type bilayer MoS₂ field-effect transistors for ultrahigh current density

The foundry industry and academia are confronting the limits of Moore's Law scaling for logic transistors. Silicon field‑effect transistors (FETs) now rely on gate‑all‑around structures and ultrathin channels, even at the cost of decreased carrier mobility and complex fabrication processes. Two‑dimensional (2D) semiconductors offer a promising alternative because they retain their crystalline quality at atomic thicknesses. Nonetheless, whether they truly exhibit higher performance than silicon remains questionable. Here, by implementing a dual‑gate structure on bilayer MoS₂ FETs, we mitigate the fringing‑field barrier created by the elevated top contact and achieve high carrier densities without increasing fabrication complexity. Simulations and statistical analysis confirm that the dual‑gate compensates the fringe field, enabling a drain current of 1.55 mA µm^-1 even with conventional gold contacts. Quantum‑transport simulation indicates that, with further gate‑length and equivalent‑oxide‑thickness scaling, the on-state current can reach levels comparable to silicon FETs at the 3-nm node, and monolithic 3D integration can extend the applicability of dual‑gate 2D transistors to future logic technologies.