An FPGA-Based Reconfigurable Accelerator for Real-Time Affine Transformation in Industrial Imaging Heterogeneous SoC

Area of Science:

• Computer Engineering
• Image Processing
• Hardware Acceleration

Background:

• Real-time affine transformation is crucial for industrial image processing but computationally intensive.
• Existing methods struggle with high interpolation costs and inefficient data access.

Purpose of the Study:

• To propose a novel reconfigurable accelerator architecture for efficient real-time affine transformation.
• To address computational bottlenecks in industrial camera and scanner image correction and registration.

Main Methods:

• Developed a heterogeneous system-on-chip (SoC) architecture decoupling control (ARM core) and data paths (FPGA).
• Implemented the proposed PATRM algorithm utilizing multiplication-free design, Q15.16 fixed-point computation, and AXI4 burst transmission.
• Employed efficient block data prefetching and pipelined processing for enhanced throughput.

Main Results:

• Achieved 25 frames per second (FPS) for high-resolution images (2095×2448), yielding a throughput of 128.21 M pixel/s.
• Demonstrated a 5.3x speedup compared to the Block AT baseline.
• Maintained a peak signal-to-noise ratio (PSNR) exceeding 26 dB.

Conclusions:

• The proposed accelerator meets real-time requirements for industrial scanner correction and other demanding image processing tasks.
• The architecture offers low resource consumption and dynamic reconfigurability.
• The PATRM algorithm significantly improves performance and efficiency for affine transformations.