Highly hardware-efficiency implementation for W-band PAM8 signal reception with additive powers-of-two quantization.

Area of Science:

• Digital Signal Processing
• Wireless Communication Systems
• Field-Programmable Gate Arrays (FPGAs)

Background:

• High-speed digital signal processing is crucial for modern wireless communication.
• Existing quantization methods for signal processing on FPGAs can be resource-intensive.
• Efficient implementation of Pulse Amplitude Modulation (PAM) schemes is essential for increasing data rates.

Purpose of the Study:

• To develop a hardware-efficient post-equalization technique for PAM8 signals.
• To implement this technique on an FPGA platform using an additive power-of-two (APoT) quantization scheme.
• To evaluate the performance and resource efficiency of the proposed APoT scheme.

Main Methods:

• Utilized an additive power-of-two (APoT) quantization scheme for post-equalization.
• Implemented the scheme on a Field-Programmable Gate Array (FPGA) platform.
• Conducted a 300-m W-band wireless communication experiment to validate the system.

Main Results:

• Achieved over 70% reduction in hardware resource consumption compared to conventional methods.
• Successfully transmitted 22.1184 Gbit/s PAM8 signals, meeting the 2.4 × 10^-2 soft-decision forward error correction (SD-FEC) standard.
• Demonstrated APoT scheme performance equivalent to 16-bit uniform quantization with superior stability.

Conclusions:

• The APoT quantization scheme offers a hardware-efficient solution for PAM8 signal post-equalization on FPGAs.
• This approach significantly reduces resource utilization without compromising critical performance metrics.
• The proposed method is suitable for high-speed W-band wireless communication systems.