Surface-enhanced thermal dissipation in 3D vertical resistive memory arrays with top selector transistors

Area of Science:

• Semiconductor device physics
• Artificial intelligence hardware
• Thermal management in electronics

Background:

• 3D memory integration, like high-bandwidth memory (HBM), boosts AI accelerator performance.
• Stacked 3D memory structures impede heat dissipation, causing thermal issues.
• Resistive random-access memory (RRAM) offers energy efficiency but faces thermal challenges in stacked arrays.

Purpose of the Study:

• To analyze the impact of selector transistor configurations on thermal accumulation in 3D RRAM.
• To investigate methods for mitigating heat generation during AI computations in neuromorphic systems.
• To enhance the thermal management and reliability of densely stacked memory layers.

Main Methods:

• Comparative analysis of selector transistor configurations in microfabricated 3D RRAM structures.
• Utilizing power parameters derived from experimental RRAM devices.
• Employing finite-element simulations and numerical calculations for thermal analysis.

Main Results:

• Optimal placement of selector transistors at the memory interface reduced nanoscale heat accumulation by up to 11%.
• Simulations verified significant reductions in peak local temperatures, from over 160 °C to below 60 °C within 20 nanoseconds.
• Effective thermal management was demonstrated in configurations with 10 to 100 stacked layers.

Conclusions:

• Selector transistor positioning is critical for thermal management in 3D RRAM for AI.
• Improved thermal design enhances power efficiency and reduces computational errors in neuromorphic computing.
• This research provides a pathway for more reliable and efficient stacked memory architectures.