Hysteresis Engineering in 2D Field-Effect Transistors

Recent advancements in field-effect transistors (FETs) based on atomically thin 2D semiconductors have demonstrated remarkable progress. These materials leverage unique physical properties and enable diverse applications beyond conventional silicon electronics, positioning them as promising candidates for extending Moore's Law. However, practical implementation of 2D FETs still faces several challenges, including scalable large-area synthesis, high contact resistance, ambient sensitivity, short-channel effects, and operational instability. The presence of hysteresis in such FETs could indicate the involvement of performance-degrading factors, such as defect-induced trap states, nonoptimal interfaces, environmental instability, and threshold voltage drift. This review examines recent advances in understanding and controlling hysteresis in 2D FETs, focusing on its physical origins, suppression strategies, and functional applications. We also emphasis the role of hysteresis in device performance, methods for its controlled exploitation, and its behavior in FETs based on emerging 2D semiconductors. We anticipate that combining the unique advantages of emerging 2D semiconductors with established device engineering methodologies will accelerate the development of next-generation transistors, enabling compact, high-density, high-performance, and multifunctional integrated electronics.