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Inverse Lithography Technology (ILT) Under Chip Manufacture Context.

Xiaodong Meng1,2, Cai Chen2, Jie Ni2

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|January 28, 2026
PubMed
Summary

Inverse lithography technology (ILT) offers superior patterning accuracy and adaptability for advanced chip manufacturing, overcoming limitations of traditional optical proximity correction (OPC). This review systematically summarizes ILT

Keywords:
computational lithographyinverse lithography technologypattern fidelityprocess window

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Area of Science:

  • Semiconductor Manufacturing
  • Computational Lithography
  • Optical Engineering

Background:

  • Advanced semiconductor nodes (3 nm and beyond) face patterning precision challenges due to sub-wavelength lithography limits.
  • Traditional optical proximity correction (OPC) and resolution enhancement technologies (RETs) are insufficient for next-generation chip manufacturing.
  • Inverse lithography technology (ILT) emerges as a critical solution within computational lithography.

Purpose of the Study:

  • To provide a systematic review of Inverse Lithography Technology (ILT) from an Electronic Design Automation (EDA) industry perspective.
  • To integrate scattered research on ILT into a coherent framework for academic and industrial utilization.
  • To analyze ILT's development, applications, challenges, and future prospects in advanced chip manufacturing.

Main Methods:

  • Explanation of ILT working principles, including concepts, mathematical formulations, and level-set/pixelated approaches.
  • Historical overview of ILT development, highlighting key advancements.
  • Analysis of current industry applications, such as hotspot fixing and EUV lithography use.

Main Results:

  • ILT offers superior patterning accuracy compared to OPC, utilizing precise optical models to correct complex lithographic issues.
  • ILT provides a wider process window by optimizing mask designs through reverse engineering from target wafer patterns.
  • ILT demonstrates enhanced adaptability for emerging lithography scenarios like High-NA EUV and extended DUV nodes.

Conclusions:

  • Key ILT bottlenecks include high computational complexity, mask manufacturing difficulties, model calibration challenges, and slow market adoption.
  • Future directions involve hybrid ILT-OPC-SMO strategies, enhanced model accuracy, AI/ML integration, and GPU acceleration.
  • This review offers a comprehensive understanding of ILT's technical landscape, promoting its industrial adoption for advanced chip manufacturing.