Total Ionizing Dose Effect Simulation Study on 130 nm CMOS Processor

Area of Science:

• Semiconductor device physics
• Radiation effects in electronics
• Integrated circuit design

Background:

• Total ionizing dose (TID) effects pose a significant threat to the reliability of microelectronic devices.
• Understanding TID-induced leakage current in transistors is crucial for predicting system-level failures.
• SMIC 130 nm bulk CMOS technology is widely used in various applications, necessitating radiation performance analysis.

Purpose of the Study:

• To perform a system-level simulation of TID effects on a SMIC 130 nm LEON2 processor.
• To develop a compact model for NMOS transistors accounting for TID-induced leakage current.
• To determine the processor's failure threshold, failure mechanism, and power supply current behavior under irradiation.

Main Methods:

• Device-level simulations using Sentaurus TCAD for 130 nm NMOS transistors.
• Development of a Verilog-A compact model for TID-induced leakage current.
• Integration of the compact model into the SPICE netlist for system-level simulations of the LEON2 processor.

Main Results:

• The study identified the failure threshold and failure mechanism of the LEON2 processor under TID.
• An increase in power supply current with increasing irradiation dose was observed.
• The developed compact model accurately describes TID-induced leakage current in NMOS transistors.

Conclusions:

• The system-level simulation approach provides valuable insights into the radiation performance of 130 nm bulk CMOS processors.
• The findings can guide radiation performance evaluation and the implementation of radiation hardening by design (RHBD) strategies.
• Accurate compact modeling is essential for predicting system-level radiation effects.