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Related Experiment Video

Updated: Jan 31, 2026

Author Spotlight: Real-Time Imaging of Bonding in 3D-Printed Layers

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Published on: September 1, 2023

3D LineExplore: a 3D line exploration method for multi-layer PCB geometric routing.

Niannian Sun¹, Jixin Zhang², Ning Xu³

¹School of Computer Science, Hubei University of Technology, Wuhan, 430068, China.

Scientific Reports

|January 29, 2026

Summary

A new 3D geometric routing method, 3D LineExplore, enhances multi-layer Printed Circuit Board (PCB) design. This advanced approach improves routing success rates and efficiency, overcoming limitations of traditional grid-based and 2D methods.

Keywords:

3D Exploration points Gridless Heuristic cost function Radar scanning

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Area of Science:

Electrical Engineering
Computer Science
Computational Geometry

Background:

Printed Circuit Board (PCB) routing complexity is increasing with advanced electronics.
Current multi-layer PCB routing methods (e.g., A*) face grid resolution limits and high computational costs.
Existing grid-less methods are often restricted to 2D, inadequate for multi-layer designs.

Purpose of the Study:

To introduce a novel 3D line-exploration-based geometric routing method for multi-layer PCBs.
To overcome grid resolution constraints and enhance routing efficiency.
To provide native support for complex multi-layer routing scenarios.

Main Methods:

A 'radar'-inspired scanning algorithm identifies optimal exploration points based on design rules and obstacles.
An obstacle-avoidance heuristic path optimization algorithm plans efficient paths, including layer transitions.
A multi-pin net repair and wire-shape optimization module ensures routing capability and path smoothness.

Main Results:

The proposed 3D LineExplore method achieved over 98% routing success on an open-source PCB dataset.
Demonstrated shorter wire lengths and higher efficiency compared to state-of-the-art methods.
Outperformed commercial tools like FreeRouting, ELECTRA, DeepPCB, and Optimized-3D-A*.

Conclusions:

The 3D LineExplore method effectively addresses challenges in multi-layer PCB routing.
Offers a superior alternative to existing grid-based and 2D grid-less approaches.
Significantly improves routing success, efficiency, and path quality in complex PCB designs.