Overcoming quadratic hardware scaling for a fully connected digital oscillatory neural network

Area of Science:

• Neuromorphic Engineering
• Digital Circuit Design
• Computational Neuroscience

Background:

• Oscillatory neural networks (ONNs) offer potential for parallel and energy-efficient computing.
• Previous ONN research focused on analytical or analog implementations.
• Digital ONN architectures face scaling challenges, particularly in hardware complexity.

Purpose of the Study:

• To investigate and propose novel digital architectures for oscillatory neural networks (ONNs).
• To address the hardware scaling limitations of existing recurrent digital ONN designs.
• To evaluate the performance and resource utilization of different digital ONN architectures on FPGAs.

Main Methods:

• Developed and analyzed a novel hybrid digital ONN architecture balancing serialization and parallelism.
• Compared the hybrid architecture against a recurrent digital ONN design.
• Emulated digital ONN architectures on a Zynq-7020 FPGA, assessing time-to-solution and resource usage.
• Quantified hardware scaling with network size and evaluated bit precision for weights and phases.

Main Results:

• The proposed hybrid architecture demonstrates near-linear hardware scaling (approx. 1.2) with network size, overcoming the quadratic scaling of recurrent designs.
• Achieved a 10.5x increase in oscillator count on an FPGA using 5-bit weights and 4-bit phases.
• Presented the largest fully connected digital ONN to date with 506 oscillators.
• Evaluated trade-offs between time-to-solution and resource utilization for different architectures.

Conclusions:

• The novel hybrid architecture represents a significant advancement for scaling digital ONNs.
• This work paves the way for implementing large-scale, energy-efficient neuromorphic computing systems using digital ONNs.
• The FPGA emulation validates the practical feasibility and efficiency of the proposed digital ONN design.