Two-Dimensional Dynamic Logic Resource Allocation for Scalable RIS Channel Emulation.

Area of Science:

• Telecommunications Engineering
• Wireless Communication Systems
• Network Resource Management

Background:

• Massive Reconfigurable Intelligent Surface (RIS)-assisted environments present significant scalability challenges for Hardware-in-the-Loop (HIL) channel emulation.
• Conventional static resource allocation designs suffer from port underutilization and path-level sparsity.

Purpose of the Study:

• To propose and evaluate a novel Two-Dimensional Dynamic Logic Resource Allocation (2D-DLRA) architecture for scalable HIL channel emulation in massive RIS-assisted 6G environments.
• To overcome the inefficiencies of static designs by decoupling physical RF ports from baseband processing resources.

Main Methods:

• Development of a Two-Dimensional Dynamic Logic Resource Allocation (2D-DLRA) architecture with hierarchical pooling at session and multipath levels.
• Joint virtualization of Logical Units (LUs) and Multipath Processing Units (MPUs).
• Analytical framework combining hierarchical queuing theory and non-cooperative game theory.

Main Results:

• The 2D-DLRA architecture achieves a multi-fold increase in supported user capacity under a 1% blocking probability QoS constraint compared to static allocation.
• 91.8% of users meet a 3% end-to-end emulation error threshold, versus 73.6% with static architectures.
• Dynamic pooling results in near-saturated hardware utilization, contrasting with single-digit utilization in static designs for sparse RIS scenarios.

Conclusions:

• The 2D-DLRA architecture offers a scalable and hardware-efficient solution for large-scale RIS channel emulation.
• The proposed architecture provides practical design guidelines for next-generation 6G HIL testing platforms.
• Dynamic resource allocation is key to optimizing performance and utilization in advanced wireless testbeds.