van der Waals dielectrics for threshold engineering in two-dimensional field effect transistors.

Area of Science:

• Materials Science
• Semiconductor Physics
• Nanotechnology

Background:

• Two-dimensional (2D) semiconductors are key for next-generation field-effect transistors (FETs).
• Current 2D FET integration into complementary-metal-oxide-semiconductors (CMOS) logic faces challenges due to improper threshold voltages (Vt), causing high power consumption.
• Existing research focused on gate electrostatics and subthreshold swing (SS), neglecting systematic Vt engineering.

Purpose of the Study:

• To investigate high-κ van der Waals (vdW) dielectrics for threshold voltage (Vt) tuning in 2D FETs.
• To explore bimetallic thiophosphates for programmable and non-volatile Vt tuning.
• To realize efficient 2D CMOS logic with reduced power consumption.

Main Methods:

• Investigated high-κ vdW dielectrics: metal oxyhalides (LaOBr, BiOBr, BiOCl) and bimetallic thiophosphates (LiInP2S6 (LIPS), LiInP2Se6 (LIPSe), CuInP2S6 (CIPS)).
• Demonstrated programmable and non-volatile Vt tuning in n-type monolayer MoS2 and p-type bilayer WSe2 FETs using bimetallic thiophosphates.
• Implemented ion-mediated Vt tuning for 2D CMOS inverters and combined experimental results with SPICE modeling.

Main Results:

• Bimetallic thiophosphates enabled programmable and non-volatile Vt tuning in both n-type MoS2 and p-type WSe2 FETs.
• Achieved nearly three orders of magnitude reduction in static power for 2D CMOS inverters while maintaining high switching speed.
• Identified an optimal Vt window for minimizing power with negligible delay, enabling built-in power gating.

Conclusions:

• Bimetallic thiophosphates offer a novel approach for effective Vt engineering in 2D FETs.
• Ion-mediated Vt tuning using these materials significantly enhances power efficiency in 2D CMOS logic.
• The findings pave the way for improved power-performance-area metrics in future electronic devices without additional sleep transistors.