3D-integrated photonic-electronic co-designed 4 × 160 Gb/s low-power high-density silicon photonic receiver with...

We present a 3D-integrated silicon photonic receiver that leverages microring-resonator (MRR) filtering and photonic-electronic co-design in a chip-on-board (CoB) flip-chip assembly. The four-channel receiver supports an aggregate data rate of 640 Gb/s, with each MRR exhibiting a full width at half maximum of ∼0.46 nm (∼57.5 GHz). By employing inductive peaking and equalization, the optical-to-electrical (O-E) 3 dB bandwidth reaches 43 GHz. Open eye diagrams are demonstrated for 160 Gb/s four-level pulse-amplitude-modulation (PAM-4) signaling, achieving receiver sensitivities of -2.25 dBm under the KP4-FEC threshold (PAM-4). The architecture attains an energy efficiency of 0.83 pJ/bit and a bandwidth density of 426.7 Gb/s/mm², comparing favorably with state-of-the-art receivers. Furthermore, a clean 200 Gb/s eye diagram is experimentally observed, underscoring the scalability of this approach for next-generation optical I/O in xPU packages and inter-chip interconnects, with potential to extend to 200 Gb/s per lane through further optimization.