HCCA-SAFE: A Hybrid Cascaded Control Architecture for FPGA-Based Fault Injection in Safety-Critical Automotive SoCs

Area of Science:

• Electrical Engineering
• Computer Engineering
• Semiconductor Device Physics

Background:

• Automotive System-on-Chips (SoCs) require rigorous functional safety verification (e.g., ISO 26262) to ensure reliability against hardware faults.
• FPGA-based fault injection is a cost-effective verification method, but traditional instrumentation approaches struggle with the high fault densities in modern automotive SoCs.
• Scalability and timing performance are critical limitations of existing fault injection techniques for complex SoCs.

Purpose of the Study:

• To propose a novel Hybrid Cascaded Fault-Injection Controller Architecture (HCCA-SAFE) addressing the scalability and timing challenges of fault injection in automotive SoCs.
• To improve the efficiency and robustness of functional safety verification for complex embedded systems.
• To reduce net delay and control-signal fanout while maintaining accuracy compared to software simulations.

Main Methods:

• Development of the HCCA-SAFE architecture, featuring constrained enable-signal cluster widths and distributed control across cascaded stages.
• Implementation and evaluation of HCCA-SAFE on multiple open-source RISC-V processor cores (openE902, openE906, openC906).
• Comparison of HCCA-SAFE's performance (net delay, fanout, speed-up) against conventional centralized and shift-chain fault injection methods and software-based RTL simulation.

Main Results:

• HCCA-SAFE significantly reduced net delay on openE902 (from 27.276 ns to 22.535 ns) and improved upon existing methods by 32.2% and 63.8%.
• On openE906 and openC906, HCCA-SAFE demonstrated substantial reductions in net delay and maximum control-signal fanout compared to conventional approaches.
• Achieved significant speed-up factors (127× to 2123×) with results consistent with software-based RTL simulation, indicating high efficiency and accuracy.

Conclusions:

• The proposed HCCA-SAFE architecture offers a scalable and timing-robust solution for fault-injection control in large automotive SoCs.
• HCCA-SAFE effectively mitigates scalability issues associated with high fault densities and improves overall verification performance.
• The architecture provides a practical and efficient method for meeting stringent functional safety standards in automotive electronics.