A Joint Parallel Timing Recovery Loop with Low Complexity for Terahertz Communication System and Its FPGA...

Area of Science:

• Electrical Engineering
• Signal Processing
• Wireless Communication

Background:

• Terahertz (THz) communication systems require efficient timing recovery for high-speed data transmission.
• Existing timing recovery loops often face challenges with large bandwidths and limited hardware resources.

Purpose of the Study:

• To propose a low-complexity joint parallel timing recovery loop for large-bandwidth THz communication systems.
• To address the shortage of on-board resources in high-speed THz systems.

Main Methods:

• A joint parallel timing recovery loop combining a modified matched filter (MMF) and a timing error detector (TED).
• Sampling point offset correction via parallel data caches (DCs).
• Timing phase error compensation by sliding MMF coefficients.

Main Results:

• The loop demonstrated efficient operation with less than 0.1 dB performance loss compared to theoretical bit error rate (BER) curves.
• Successful parallel demodulation of 15 Gbps 64QAM signals at 220 GHz on a THz FPGA platform.
• Significant reduction in hardware resource consumption.

Conclusions:

• The proposed loop is a viable solution for high-speed THz communication systems.
• It effectively balances performance and resource efficiency.
• The implementation validates its practical applicability in demanding communication environments.