Optimized fault-tolerant data processing module for high-reliability CNN accelerator.

Area of Science:

• Computer Engineering
• Hardware Architecture
• Artificial Intelligence

Background:

• Convolutional neural networks (CNNs) are crucial for image inference.
• Systolic array architectures offer high performance but face hardware overhead and reliability challenges.
• Existing processing elements (PEs) in these systems present a trade-off between efficiency and reliability.

Purpose of the Study:

• To propose a novel module for PEs that enhances both efficiency and reliability.
• To reduce power consumption and hardware footprint in systolic array systems.
• To minimize testing overhead and improve fault detection capabilities.

Main Methods:

• Integration of local binary patterns and min-max operations within PE modules.
• Reutilization of optimized architecture for efficient fault detection.
• Implementation of a fault-PE bypass mechanism for robust system operation.

Main Results:

• A 29.03% reduction in hardware area using the Nan Gate 45nm library.
• A 13.72% decrease in dynamic power consumption on a field-programmable gate array.
• Up to 33.57% error reduction and over 94% test coverage in fault-injection experiments.

Conclusions:

• The proposed module significantly improves PE efficiency and reliability.
• This approach offers a practical solution to the hardware overhead and reliability trade-offs in systolic arrays.
• The module enhances CNN hardware acceleration with reduced power and area.