Subtractive-Dither-Assisted Background Calibration for Linearity Enhancement in Pipelined ADCs for IIoT Applications

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Signal Processing

Background:

• Pipelined analog-to-digital converters (ADCs) are crucial for high-speed data acquisition.
• Nonlinearities in ADCs, such as differential nonlinearity (DNL) and integral nonlinearity (INL), degrade performance.
• Traditional calibration methods can be complex and power-intensive.

Purpose of the Study:

• To present a subtractive-dither-assisted background calibration technique for a 2 GS/s 12-bit pipelined ADC.
• To improve the spurious-free dynamic range (SFDR) by decorrelating nonlinearity errors.
• To evaluate the impact of dithering on signal-to-noise-and-distortion ratio (SNDR) and static linearity.

Main Methods:

• Injection of a 7-bit pseudo-random dither into the flash and multiplying digital-to-analog converter (MDAC) stages.
• Design and simulation of the ADC in a 28 nm CMOS process with a 1 V supply.
• Post-layout simulations to assess performance improvements under near-Nyquist input frequencies.

Main Results:

• A 10.2 dB improvement in SFDR, from 73.8 dB to 84.4 dB, was achieved with dithering.
• Signal-to-noise-and-distortion ratio (SNDR) degradation was minimal (0.5 dB), resulting in 62.3 dB and 10.1 effective bits (ENOB).
• Static linearity improved, with DNL and INL optimized to ±0.54 LSBs and ±0.88 LSBs, respectively.
• The dither-based calibration introduced less than 2 mW of additional power consumption.

Conclusions:

• The subtractive-dither-assisted background calibration technique effectively enhances ADC SFDR.
• The method offers a low-power solution for improving ADC linearity without significant SNDR penalty.
• This technique is suitable for high-speed, high-resolution ADC applications in advanced CMOS processes.