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Investigation of Resistive Switching in Cu/a-SiC/P+-Si Structure for Multilevel Nonvolatile Memory Applications
Hehong Shao1, Xiuwei Zhu1, Xin Zhang1
1School of Biomedical Engineering, National Engineering Research Center of Ophthalmology and Optometry, Eye Hospital, Wenzhou Medical University, Wenzhou 325027, China.
This study explores resistive switching in a copper/amorphous silicon carbide/P+-silicon device for multilevel memory. The device demonstrates four distinct resistance states and reliable data retention up to 85°C, showing promise for RRAM applications.
Area of Science:
- Materials Science
- Electrical Engineering
- Nanotechnology
Background:
- Resistive switching (RS) memory devices offer promising alternatives to conventional memory technologies.
- Multilevel nonvolatile memory is crucial for high-density data storage.
- Conducting filament formation is a key mechanism in many RS devices.
Purpose of the Study:
- To investigate the resistive switching characteristics of a Cu/a-SiC/P+-Si device.
- To explore the potential of this structure for multilevel nonvolatile memory applications.
- To understand the role of conducting filament formation in the switching mechanism.
Main Methods:
- Fabrication of a Cu/a-SiC/P+-Si sandwiched structure.
- Systematic investigation of resistive switching behavior.
- Temperature-dependent testing to elucidate the switching mechanism.
- Modulation of compliance current to achieve multiple resistance states.
Main Results:
- Achieved four distinct resistance states in the Cu/a-SiC/P+-Si memory device.
- Identified copper conducting filament formation as the switching mechanism.
- Demonstrated reliable data retention of approximately 10^5 seconds at temperatures up to 85 °C.
- Showed that higher compliance current during the Set process leads to more conductive filaments.
Conclusions:
- The Cu/a-SiC/P+-Si device exhibits promising multilevel resistive switching characteristics.
- The device shows potential for high-density RRAM applications due to its reliable retention and multilevel capability.
- Understanding filament formation is key to optimizing device performance.
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