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Fast Decoupled and DC Powerflow

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The fast decoupled power flow method addresses contingencies in power system operations, such as generator outages or transmission line failures. This method provides quick power flow solutions, essential for real-time system adjustments. Fast decoupled power flow algorithms simplify the Jacobian matrix by neglecting certain elements, leading to two sets of decoupled equations:
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Linearization is a mathematical technique used to approximate complex, nonlinear functions with simpler linear models in the vicinity of a chosen reference point. The method is based on the idea that, although a function may be difficult to evaluate exactly, its behavior near a specific input value can often be closely approximated by the tangent line at that point. This approach is particularly useful when small deviations from a known value are involved.Consider the square root function, for...
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Related Experiment Videos

FLASH: Energy-Efficient FPGA Acceleration via Linear Approximation and Streamlined Two-Stage Pipeline Architectures

Nam Joon Kim, Beom Jin Kang, Hae In Lee

    IEEE Transactions on Neural Networks and Learning Systems
    |April 1, 2026
    PubMed
    Summary

    We developed FLASH, an FPGA accelerator for Hybrid Vision Transformers (HybridViTs). FLASH significantly reduces power consumption and improves energy efficiency for real-time computer vision tasks on edge devices.

    Related Experiment Videos

    Area of Science:

    • Computer Vision
    • Hardware Acceleration
    • Deep Learning

    Background:

    • Hybrid Vision Transformers (HybridViTs) combine CNNs and Transformers for superior feature extraction.
    • Computational asymmetry between CNN and Transformer blocks hinders hardware optimization.
    • Existing hardware solutions struggle with efficient acceleration of HybridViTs.

    Purpose of the Study:

    • To propose FLASH, a power-efficient FPGA-based accelerator for HybridViT models.
    • To address the challenges of optimizing and accelerating CNN-Transformer hybrid networks on a single hardware architecture.
    • To enable real-time inference of HybridViTs on edge devices with minimal accuracy loss.

    Main Methods:

    • FLASH employs a two-stage pipeline architecture on an FPGA.
    • It reduces quantization overhead via requantization and enables 8-bit integer computation.
    • Hardware-friendly approximations for nonlinear functions and optimized dataflow are utilized.

    Main Results:

    • FLASH achieves minimal accuracy drop (0.84%) on ImageNet-1K for MobileViT (MViT)-xxs.
    • It demonstrates up to 16.8x lower power consumption compared to CPU/GPU.
    • FLASH offers a 26.3x improvement in energy efficiency.

    Conclusions:

    • FLASH is an effective energy-efficient hardware accelerator for HybridViT models.
    • It enables real-time inference on edge devices with significant power and energy savings.
    • The proposed techniques overcome computational asymmetry challenges in HybridViTs.