Scalable Reconfigurable Circuits with Double-Gate MoS₂ Transistors.

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Reconfigurable transistors are key for versatile logic circuits, but current designs face reliability, fabrication, and voltage mismatch challenges.
• Increased device complexity in existing reconfigurable devices hinders cascadability and scalability for practical applications.

Purpose of the Study:

• To propose a cascadable reconfigurable logic unit based on MoS₂ double-gate transistors (DGFETs).
• To overcome limitations of existing reconfigurable devices, enabling large-scale fabrication and improved functionality.

Main Methods:

• Utilized MoS₂ double-gate transistors (DGFETs) compatible with conventional integration processes.
• Implemented double-gate tuning and resistive voltage division for multiple logic functions.
• Demonstrated a 10x10 array, the largest to date for 2D reconfigurable transistors in logic.

Main Results:

• Achieved four distinct logic functions using only an n-type channel with matched input/output voltage ranges.
• Successfully fabricated cascaded reconfigurable circuits with XOR/XNOR functions.
• Demonstrated real-time switching between half-subtractor and comparator operations.

Conclusions:

• The proposed MoS₂ DGFET logic unit offers a viable and practical approach for scalable integration of reconfigurable transistors.
• This work advances the development of high-efficiency, high-versatility logic circuits for future electronic systems.