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Updated: Apr 4, 2026

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology
Published on: December 7, 2015
Filled Carbon Nanotube Ternary Transistors
Yu Teng1,2,3, Jian Yao1,2, Qinan Wang2,4
1School of Nano-Tech and Nano-Bionics, University of Science and Technology of China, Hefei, P. R. China.
Abstract:
As circuit integration continues to advance, power consumption has become a critical bottleneck limiting further development. Multi-valued logic (MVL) has garnered extensive attention due to its potential to reduce interconnect complexity and switching losses. Single-walled carbon nanotubes (SWCNTs), with their superior electrical properties, ultra-small dimensions, and controllable aligned array growth, offer unique advantages for the large-scale fabrication of high-density MVL circuits. However, progress in this field using SWCNTs remains relatively lagging compared to two-dimensional materials, primarily due to device stability issues arising from challenges in precise doping control. Here, we demonstrate a system consisting of acetylacetonate metal molecules encapsulated within SWCNTs (M(acac)x@s-SWCNT), in which carrier concentration can be dynamically modulated under an applied electric field. Transistors based on this platform validate that this electric-field-controlled modulation yields three well-defined logic states: 0, 1, and 2. These transistors demonstrate good uniformity and stable operation, showing a static power consumption of 8.2 pW and dynamic power consumption of 0.31 nJ (state 0 to 1) and 0.35 µJ (state 1 to 2). The ternary inverter based on this heterostructure exhibits rail-to-rail output capability, enabling the accurate execution of MVL operations. Ternary weight networks (TWNs) built with these transistors reduce computational complexity and storage, enabling efficient neuromorphic computing.
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