Impact of material and structural parameters on the performance of advanced low-power CNTFET-based SRAM designs

This paper comprehensively evaluates the efficiency of various Carbon Nanotube Field-Effect Transistor (CNTFET)-based static random-access memory (SRAM) cell topologies, including 6T, 8T, 10T, and a modified 10T SRAM design. By employing low-power approaches and utilizing Cadence Virtuoso at 32 nm technology, we explore the impact of tube diameter and dielectric constants on the performance of these SRAM cells. Simulation findings reveal that employing an 8T SRAM cell leads to a 26.5% reduction in write delay and a 28.75% decrease in read delay using silicon dioxide(SiO₂) as the gate dielectric material (dielectric constant, k=3.9) when CNT tube diameter varies between 1.0179 nm and 1.6443 nm . Further investigations indicate that varying dielectric constants (ranging from 3.9 to 30) while maintaining a constant tube diameter of 1.95575 nm yields a 13.08% reduction in write delay, a 12.13% decrease in read delay, a 2.16% increase in power consumption, and an 11.20% drop in thepower delay product (PDP) value. Through a comprehensive analysis of 6T, 8T, 10T, and 10T (modified) SRAM cells, the modified 10T SRAM cell, with separate paths for read and write operations, exhibits reduced delay and a lower PDP value compared to other SRAM designs.Optimizing tube diameter and utilizing the high carrier mobility of Carbon Nanotubes (CNTs) significantly enhance the performance of SRAM cells. This optimization enables faster switching speeds and reduced propagation delays, making CNTFET-based SRAM cells a promising option for low-power memory devices at the 32 nm technology node.