Related Experiment Video
Updated: Apr 10, 2026

04:57
Residue-Free Fabrication of van der Waals Heterostructures of Two-Dimensional Materials
Published on: July 18, 2025
1.4K
Manipulating MoS2 Thickness On-Chip via Van Der Waals Delamination
Zehao Li1, Yunxin Li1, Xiao Liu1
1School of Physics and Electronics, Key Laboratory for Micro-Nano Optoelectronic Devices of Ministry of Education, Hunan University, Changsha, China.
Small Methods
|April 9, 2026
Summary
This study introduces a novel on-chip van der Waals etching method to precisely control the thickness of 2D semiconductor flakes like MoS2. This technique allows for atomic-layer precision, enabling tailored electronic properties for advanced devices.
Area of Science:
- Materials Science
- Nanotechnology
- Condensed Matter Physics
Background:
- Thickness of 2D semiconductors critically impacts electronic properties like bandgap and carrier mobility.
- Current methods for producing 2D materials, such as mechanical peeling, lack control over flake thickness.
- Van der Waals (vdW) heterostructures require precise control over layer thickness for optimal device performance.
Purpose of the Study:
- To develop a low-energy, on-chip method for precisely manipulating the thickness of 2D semiconductor flakes.
- To enable re-peeling of 2D flakes after initial exfoliation with atomic-layer precision.
- To investigate the influence of metal-flake interactions on the etching process and resulting thickness control.
Main Methods:
- A novel on-chip van der Waals etching technique utilizing metal peeling to physically remove top layers of 2D flakes.
- Controlled manipulation of the interaction force between 2D flakes (e.g., MoS2) and metals on a substrate.
- Atomic force microscopy (AFM) for surface characterization and roughness analysis.
- Mechanical modeling to explain the etching mechanism based on competing forces.
Main Results:
- Demonstrated a low-energy vdW etching approach for on-chip thickness control of 2D materials.
- Achieved atomically flat etched surfaces with significantly lower roughness (0.21 nm) compared to plasma etching (1.26 nm).
- Showcased thickness control ranging from 2 nm to over 50 nm by varying the on-chip metals used.
- Validated that intrinsic properties of the remaining 2D layers are well preserved during etching.
Conclusions:
- The developed vdW etching method offers a precise and low-energy solution for on-chip thickness control of 2D semiconductors.
- This technique overcomes the limitations of conventional methods, enabling tailored electronic properties for 2D material-based devices.
- The findings provide a new pathway for fabricating advanced van der Waals heterostructures with designed functionalities.
More Related Videos
Related Concept Videos
MOSFET: Depletion Mode
1.1K
Depletion-mode MOSFETs represent a unique subset of MOSFET technology, functioning fundamentally differently from their enhancement-mode counterparts. Unlike enhancement MOSFETs, which require a positive gate-source voltage (Vgs) to turn on, depletion-mode MOSFETs are inherently conductive and "normally on" devices.
The primary characteristic of depletion-mode MOSFETs is their ability to conduct current between the drain and source terminals without gate bias. This inherent conductivity...
The primary characteristic of depletion-mode MOSFETs is their ability to conduct current between the drain and source terminals without gate bias. This inherent conductivity...
1.1K
MOSFET: Enhancement Mode
1.0K
Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
1.0K
MOS Capacitor
1.9K
A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
1.9K

