Characterising the failure mechanisms of error-corrected quantum logic gates.

Area of Science:

• Quantum Computing
• Quantum Error Correction
• Superconducting Qubits

Background:

• Mid-circuit measurements are crucial for fault-tolerant quantum computers, enabling syndrome readout and logic gate operations.
• Superconducting qubit arrays are a leading platform for developing quantum technologies.

Purpose of the Study:

• Investigate the impact of noise sources on error-corrected logic in a superconducting qubit array.
• Improve the performance of quantum memory and logic gates by addressing specific error mechanisms.

Main Methods:

• Utilized a heavy-hex code on a superconducting qubit array.
• Designed and implemented a low-depth syndrome extraction circuit.
• Conducted stability experiments to analyze readout assignment errors during logic gates.
• Performed holistic device benchmarking and numerical simulations.

Main Results:

• Idling errors during readout significantly degrade quantum memory; a low-depth syndrome extraction circuit mitigates this.
• Stability experiment error rates decrease with more stabilizer readout cycles, indicating a trade-off between stability and memory decay time.
• Measurement noise was identified as a dominant factor affecting the fidelity of fault-tolerant logic gates.

Conclusions:

• Optimizing syndrome extraction circuits is key to improving quantum memory performance.
• Careful management of readout assignment errors and stabilizer cycles is necessary for stable quantum logic operations.
• Reducing measurement noise is critical for achieving high-fidelity fault-tolerant quantum computation.