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CMOS compatible probabilistic computing hardware with cointegrated reconfigurable p-bits and synapse arrays.

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Researchers developed a novel charge-trap transistor for probabilistic computing. This device acts as both a probabilistic bit and synapse, enabling scalable hardware for solving complex optimization problems at room temperature.

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Area of Science:

  • * Novel semiconductor device physics and engineering.
  • * Exploration of probabilistic computing paradigms.
  • * Advancements in integrated circuit design for optimization problems.

Background:

  • * Probabilistic computing (p-computing) offers a room-temperature alternative to quantum computing for combinatorial optimization problems (COPs).
  • * Scalable p-computing hardware necessitates the integration of probabilistic bits (p-bits) and synapses, which have conflicting device requirements.
  • * Existing solutions face challenges in device compatibility and scalability for practical p-computing.

Purpose of the Study:

  • * To present a reconfigurable charge-trap field-effect transistor (CT-FET) capable of functioning as both a p-bit and a synapse.
  • * To demonstrate the cointegration of p-bits and synapse arrays on a single wafer using standard CMOS processes.
  • * To validate the performance of the integrated system in solving complex optimization problems.

Main Methods:

  • * Development of a CT-FET using a silicon-oxide-nitride-silicon gate stack, derived from commercial flash memory.
  • * Utilizing gate voltage control of trap energy to enable stochastic operation for p-bits and stable operation for synapses.
  • * Cointegration of p-bits and synapse arrays on a single wafer via standard CMOS fabrication processes.

Main Results:

  • * Experimental demonstration of solving a 4-node weighted max-cut problem, including negative weights.
  • * Simulated efficient solution of a 20-node weighted max-cut problem with negative weights using chaotic simulated annealing.
  • * Successful cointegration of p-bits and synapse arrays, confirming CMOS compatibility.

Conclusions:

  • * The developed CT-FET offers a reconfigurable solution for p-bits and synapses, addressing key hardware integration challenges.
  • * CMOS-compatible fabrication enables a pathway toward scalable and practical probabilistic computing processors.
  • * The technology shows promise for efficiently solving complex combinatorial optimization problems at room temperature.