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Area of Science:

  • Materials Science
  • Semiconductor Physics
  • Nanotechnology

Background:

  • Planar complementary metal-oxide-semiconductor (CMOS) scaling faces physical limitations.
  • Monolithic three-dimensional (M3D) integration using complementary field-effect transistors (CFETs) is the emerging transistor roadmap.
  • Silicon (Si)-CFETs show promise but face scalability challenges like high thermal budgets and dopant diffusion.

Purpose of the Study:

  • To explore the potential of two-dimensional (2D) materials for advanced CFET integration.
  • To address the challenges and outline the prospects of 2D material-based CFETs.
  • To compare the thermal and power efficiency of 2D-CFETs versus Si-CFETs.

Main Methods:

  • Review of 2D material synthesis and channel engineering for n- and p-type transistors.
  • Analysis of low-resistance metal contacts and gate dielectric integration for 2D materials.
  • Comparative study of heat dissipation and energy consumption in different CFET stacking configurations.

Main Results:

  • 2D materials offer low-temperature process compatibility ideal for back-end-of-line (BEOL) integration.
  • 2D materials present a pathway for overcoming Si-CFET scalability constraints.
  • 2D-CFETs are predicted to offer superior thermal and power efficiency over Si-CFETs.

Conclusions:

  • 2D materials are a promising platform for scalable and thermally efficient logic architectures in the Ångström era.
  • Addressing challenges in material synthesis, device engineering, and interconnects is crucial for realizing 2D CFETs.
  • 2D CFETs represent a viable alternative for future transistor technology beyond conventional scaling limits.