Performance optimization of a polymer-embedded dual-core slot-assisted plasmonic switch for PICs

This work presents the optimization of a slot-assisted dual-core-based plasmonic switch (SADCPS), where a polymer cladding is employed to strengthen optical confinement in the narrow slot separating the silicon waveguides. Owing to its low propagation loss, the device demonstrates enhanced extinction ratio (ER) and figure-of-merit (FOM) performance. The tailored geometry confines the optical field efficiently within the slot between the two silicon rails, supported by surrounding indium-tin-oxide (ITO) and graphene layers. At an operating wavelength of 1.55 µm, the SADCPS exhibits an ER of 30.13 dB/µm, while the graphene-based configuration achieves 21.57 dB/µm. The associated insertion losses (ILs) are 0.043 and 0.063 dB/µm, respectively. The maximum modulation speed reaches 3 THz for the SADCPS and 2 THz for the graphene-integrated design. Moreover, the 3 THz modulation rate is realized with a low energy consumption of 1.11 fJ/bit. This enhancement in performance is primarily attributed to systematic optimization of the geometrical and structural parameters of the SADCPS. Additionally, the effect of doubling the device length is also evaluated at the same operating wavelength, demonstrating that both configurations remain highly suitable for integration into next-generation photonic integrated circuit (PIC) platforms.