Secure implantable cardiac pacemaker for medical consumer electronics

This paper proposes a novel approach to design secure hardware IPs of filter bank and QRS complex for implantable cardiac pacemaker, ensuring reliability and safety of patients. The hardware IPs are designed using proposed secure high-level synthesis (HLS), beginning with the derivation of data flow graphs from their transfer functions. It then extracts the AES-encrypted security signature of the original IP vendor, which is then encoded as a covert digital proof and covertly embedded during the HLS register allocation module. This produces secured hardware IP register transfer level (RTL) designs carrying embedded digital evidence for detective countermeasure against IP piracy/counterfeiting. The results demonstrate: (a) a low probability of coincidence, signifying strength of digital proof for hardware IPs (8.40E-17 to 4.78E-3); (b) stronger tamper tolerance (1.34E + 154 to 2.41E + 462) at negligible design cost overhead; (c) improved probability of coincidence, tamper tolerance and entropy compared to other approaches for proposed pacemaker hardware IPs.