Secure implantable cardiac pacemaker for medical consumer electronics.

Area of Science:

• Biomedical Engineering
• Computer Engineering
• Cryptography

Background:

• Implantable cardiac pacemakers require secure hardware intellectual property (IP) for patient safety and reliability.
• Hardware IP piracy and counterfeiting pose significant risks to the integrity of medical devices.

Purpose of the Study:

• To propose a novel secure high-level synthesis (HLS) approach for designing filter bank and QRS complex hardware IPs for pacemakers.
• To embed a covert digital proof within the hardware designs to prevent IP piracy and counterfeiting.

Main Methods:

• Derivation of data flow graphs from transfer functions for hardware IP design.
• Extraction and AES-encryption of the IP vendor's security signature.
• Encoding the signature as a covert digital proof and embedding it during HLS register allocation.
• Generation of secure hardware IP register transfer level (RTL) designs.

Main Results:

• Demonstrated a low probability of coincidence (8.40E-17 to 4.78E-3), indicating strong digital proof.
• Achieved enhanced tamper tolerance (1.34E+154 to 2.41E+462) with negligible design cost overhead.
• Showcased improved probability of coincidence, tamper tolerance, and entropy compared to existing methods for pacemaker hardware IPs.

Conclusions:

• The proposed secure HLS method effectively embeds digital evidence to counteract IP piracy in pacemaker hardware.
• The developed technique ensures the reliability and safety of implantable cardiac pacemakers through robust security measures.
• This approach offers a cost-effective solution for securing critical hardware components in medical devices.