Machine learning enabled unique chip feature extraction approach for semicustom delay variant PUF

The article presents a chip feature extraction approach to create unique and unclonable hardware fingerprints to increase reliability in a hardware security system. A static D flip-flop-based delay counter is used as a delay unit to propose a lightweight PUF in place of the Configurable Ring Oscillators (CROs) in the existing PUF. Initially, the design is simulated and synthesized using three different Complementary Metal-Oxide-Semiconductor (CMOS) technologies to study process variations. Its reliability is ensured through Multi-Mode Multi-Corner (MMMC) analysis. The circuit stands out with its + 0.004 ps slack timing and operates stably within a temperature range of 0 °C to 125 °C. It is quite interesting to observe that it works efficiently within a voltage range of 1.62 V to 1.98 V. Overall, 155 unique data paths are resolved and carried out by Static Timing Analysis (STA), which ensures the uniqueness of the core design. Furthermore, the results of Machine Learning techniques and the NIST statistical test suite confirm the proposed structure's randomness strength. A comparison of this work with recent findings indicates the specific advantages of the implemented method. The study classifies the proposed Semicustom Delay Variant PUF (SDV PUF) as either strong or weak by adhering to the security requirements.