Analysis of Chip Electronic Components' Typical Yield in Taping Process Based on Virtual Metrology

Area of Science:

• Manufacturing Process Control
• Data Science in Engineering
• Semiconductor Manufacturing

Background:

• Virtual metrology (VM) faces challenges in electronic component taping due to partial observability and data imbalance.
• Direct batch-wise yield prediction is unstable, hindering effective process monitoring.

Purpose of the Study:

• To develop a data-centric VM framework for stable yield prediction in electronic component taping.
• To reformulate the task as predicting operating-condition-level typical yield.

Main Methods:

• Physically relevant features were identified using correlation and mutual information.
• Multidimensional equal-frequency binning created operating condition groups.
• A dictionary-based representation with low-yield-oriented sample weighting was employed.

Main Results:

• The proposed VM framework demonstrated more stable predictions than direct modeling.
• Improved tail-oriented fitting was observed compared to unweighted baselines.
• Operating condition stratification stabilized VM prediction for partially observable data.

Conclusions:

• Operating condition stratification provides a practical method for stabilizing VM prediction.
• Low-yield-oriented sample weighting enhances sensitivity to low-yield conditions.
• The framework supports early yield warning and informed process-level decision-making.