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Published on: December 7, 2017
Suppression of charge-trapping-induced hysteresis enabling hysteresis-free Te nanowire field effect transistors
Yanling Yin1, Weichang Zhou1, Dongsheng Tang1
1School of Physics and Electronics, Key Laboratory of Low-dimensional Quantum Structures and Quantum Control of Ministry of Education, Key Laboratory of Multiphysics Intelligent Materials and Devices in Hunan Provincial Universities, Hunan Province Fundamental Research Center for Quantum Effects and Quantum Technology, Hunan Normal University, Changsha 410081, China.
Abstract:
Tellurium (Te) nanowire field-effect transistors (FETs), fabricated via photolithography, exhibit p-type conduction with a high hole mobility of 155.6 cm2 V-1 s-1. However, pronounced hysteresis is observed in the transfer characteristics of the devices. Through systematic electrical and environmental regulation, this hysteresis is attributed to the combined effects of extrinsic charge traps at the nanowire/SiO2 interface and adsorbed water molecules. Critically, cryogenic (77 K) operation eliminates hysteresis while maintaining excellent performance, directly confirming the thermal activation of trap states. These findings provide material-specific guidelines for enhancing the stability of Te-based devices for applications in optoelectronics, memory, and neuromorphic computing.
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