Graph Neural Networks for Autonomous Multi-Scale Design of Optoelectronic Nanoelectronic Devices.

Area of Science:

• Computational materials science
• Machine learning for device design
• Nanoelectronics and optoelectronics

Background:

• Designing nanoelectronic devices requires multi-scale modeling, integrating atomic, mesoscopic, and device levels.
• Traditional design methods are often slow and lack autonomy.
• Graph-based representations offer a powerful way to model complex material structures.

Purpose of the Study:

• To develop an autonomous, multi-scale computational framework for designing optoelectronic nanoelectronic devices.
• To integrate physics-based constraints and quantum behavior into the design process.
• To optimize device performance metrics like quantum efficiency and structural stability.

Main Methods:

• Utilized a dataset of ~167,000 hierarchical graphs representing devices at atomic, mesoscopic, and device levels.
• Implemented three scale-specific Graph Neural Networks (GNNs) with cross-scale attention for feature fusion.
• Employed constrained reinforcement learning for topology evolution and augmented Lagrangian for multi-objective optimization.

Main Results:

• Achieved accurate energy spectrum prediction using a GNN-parameterized effective Hamiltonian with physics-regularized loss.
• Identified Pareto-consistent device configurations balancing efficiency, stability, and complexity.
• Validated selected designs using finite-element multiphysics simulations for optical and electrical consistency.

Conclusions:

• The developed framework provides a reproducible, physics-constrained pipeline for autonomous nanoelectronic device design.
• Graph-based machine learning, particularly GNNs, is effective for multi-scale device modeling and optimization.
• This approach accelerates the discovery of novel nanoelectronic device architectures.