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Overcoming Boltzmann's Tyranny in All-Metal-Oxide Negative Capacitance Field-Effect Transistor
Chan Lee1, Suhwan Hwang1,2, Jong Chan Shin1
1Department of Chemical and Biological Engineering, and Institute of Chemical Processes, College of Engineering, Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea.
None:
Negative capacitance field-effect transistors (NCFETs) have emerged as potent contenders for next-generation electronics, capable of surmounting Boltzmann's tyranny that limits the minimum subthreshold swing (SS) to 60 mV dec-1 at room temperature. Despite these advances, most precedents beyond silicon channels employ unconventional channels such as 2D van der Waals materials or 1D carbon nanotubes, whose tenuous CMOS compatibility hampers uniformity in large-scale fabrication and exacerbates concerns about reproducibility. Functional oxides, such as oxide semiconductors and high-k oxides, offer a breakthrough to these obstacles, especially with CMOS-compatible methods like atomic layer deposition (ALD). Here, we demonstrate NCFETs with all components fabricated by ALD, featuring Ga-doped HfO2 (HGO) as the ferroelectric layer, undoped HfO2 as a paraelectric buffer, and indium gallium zinc oxide (IGZO) as the channel. The fabricated devices exhibit an average SS of 46 mV dec-1 at room temperature over nearly two decades of drain current, clearly surpassing the thermionic limit. All 27 devices deliver SS values below 60 mV dec-1, attesting to device-to-device uniformity and high fidelity enabled by the ALD process. We preset the ferroelectric HGO layer and tailor the capacitance of the paraelectric buffer to ensure hysteresis-free, ultralow SS operation of the NCFET. Additionally, the NCFET successfully serves as the driver transistor in a resistive load inverter, achieving a voltage gain of 25.7 and consuming ∼18 pW μm-1 at VDD = 1 V. These findings establish an all-oxide, ALD-compatible NCFET platform that mitigates the scalability, uniformity, and reliability bottlenecks of the previous approaches and is adequate for wafer-scale, energy-efficient logic.
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