Memristor-based reconfigurable architecture for binarized neural networks: Implementation and robustness analysis.

Area of Science:

• Computer Science
• Electrical Engineering
• Materials Science

Background:

• Memristors offer in-memory and parallel computing, promising for neural network accelerators.
• Device imperfections in memristors hinder precise synaptic weight adjustment for neural networks.
• Binarized neural networks (BNNs) utilize binary weights, aligning well with memristor conductance states.

Purpose of the Study:

• Propose a memristor-based reconfigurable in-memory computing architecture for BNNs.
• Address the challenges of memristor nonlinearity and variations in implementing neural networks.
• Enable efficient and robust implementation of BNNs using memristor technology.

Main Methods:

• Designed a modular architecture combining dedicated memristor-based layers (convolutional, fully connected, batch normalization, pooling).
• Mapped binary weights to high/low memristor conductance states using an average midpoint reference.
• Employed a two-phase programming scheme for stable memristor state setting.

Main Results:

• Achieved low test errors on MNIST (1.75% for MLP, 0.73% for CNN) and CIFAR-10 (31.52% for CNN) using the memristor-based BNN architecture.
• Demonstrated robust noise tolerance: up to 20% weight noise, 30% input noise.
• Showcased fault tolerance with a 12.5% stuck-at-fault rate without significant performance degradation.

Conclusions:

• The proposed memristor-based architecture effectively implements BNNs, achieving competitive accuracy.
• The architecture exhibits significant resilience to noise and faults, crucial for real-world applications.
• Memristors are well-suited for efficient BNN acceleration, overcoming traditional device limitations.