Design of a SiC MOSFET Gate Driver Chip Based on Adaptive Active Drive Technology

Silicon carbide (SiC) MOSFETs are promising for high-efficiency, high-power-density power conversion owing to their high breakdown capability, fast switching speeds, and low switching losses. However, parasitic parameters can cause severe voltage/current overshoot and oscillation during high-speed switching, leading to electromagnetic interference and degraded performance. To address this issue, this study analyzes the mechanisms of current overshoot during turn-on and voltage overshoot during turn-off, and presents an adaptive active gate driver chip based on a three-stage driving current control strategy. By identifying key switching intervals and regulating segmented gate-drive current, the proposed chip can effectively suppress overshoot while reducing the switching loss. During turn-on, cross-cycle switching point regulation based on Miller plateau tracking is proposed to achieve adaptive control under different operating conditions, while the turn-off control is realized by peak sampling of the drain-source voltage. The chip was fabricated in the 180 nm BCD process. Compared with a conventional passive driver, the proposed driver reduces turn-on loss by 35.1% at 400 V/40 A under a dv_DS/dt of 4.8 V/ns and reduces turn-off loss by 33.2% under a v_DS overshoot of nearly 50 V. These results show that the proposed chip improves SiC MOSFET switching performance and provides a practical gate-driving solution.